CohereSim: A Bus-based Cache Simulator  v3.3
A tool for education in computing - learn about coherence protocols, replacement policies, and SMP vs DSM
memory_system.h
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1 
4 #pragma once
5 
6 #include "typedefs.h"
7 
9 #define MAX_N_CACHES 0b10000000
10 
12 class MemorySystem {
13 public:
14 
15 #ifdef WRITE_TIMESTAMP
18 
21 #endif
22 
25 
27  bool flushed;
28 
32  virtual ~MemorySystem();
33 
37 #ifdef WRITE_TIMESTAMP
39 #endif
40  void issuePrRd(addr_t addr, uint32_t cache_id
41 #ifdef WRITE_TIMESTAMP
42  , size_t read_timestamp
43 #endif
44  );
48 #ifdef WRITE_TIMESTAMP
50 #endif
51  void issuePrWr(addr_t addr, uint32_t cache_id
52 #ifdef WRITE_TIMESTAMP
53  , size_t write_timestamp
54 #endif
55  );
56 
61  virtual void issueBusMsg(bus_msg_e bus_msg, addr_t addr, uint32_t cache_id) = 0;
62 
64  void printStats();
65 
66 protected:
67 
70 
71 private:
72 
75 
76 #ifdef WRITE_TIMESTAMP
81  void verifyTimestamp(addr_t addr, bool write, size_t current_timestamp);
82 #endif
83 };
84 
87 #define ADD_DIRECTORY_TO_CMD_LINE(dir_prot) static int register_directory = []() { \
88 if (directory_map == nullptr) directory_map = new std::map<std::string, dir_factory_t, ci_less>(); \
89 (*directory_map)[#dir_prot] = [](cache_config& config) { return new dir_prot(config); }; return 0; }()
An L1 Cache with coherence protocol and replacement policy.
Definition: cache.h:9
The MemorySystem class connecting multiple caches and main memory.
Definition: memory_system.h:12
virtual void issueBusMsg(bus_msg_e bus_msg, addr_t addr, uint32_t cache_id)=0
Issue a bus message from a cache to all other caches.
void issuePrWr(addr_t addr, uint32_t cache_id, size_t write_timestamp)
Issue a PrRd message to a cache.
Definition: memory_system.cc:31
void verifyTimestamp(addr_t addr, bool write, size_t current_timestamp)
Check if all valid copies of a cache block have the same timestamp.
Definition: memory_system.cc:55
size_t access_timestamp
The access number of the current memory access.
Definition: memory_system.h:17
Cache * caches[MAX_N_CACHES]
Array of this memory system's caches.
Definition: memory_system.h:69
void printStats()
Print simulation run statistics in CSV format (headerless)
Definition: memory_system.cc:48
cache_config config
Config for this memory system.
Definition: memory_system.h:74
void issuePrRd(addr_t addr, uint32_t cache_id, size_t read_timestamp)
Issue a PrWr message to a cache.
Definition: memory_system.cc:14
bool copies_exist
Flag to indicate if copies of a cache block exist in other caches.
Definition: memory_system.h:24
size_t most_recent_sibling
The most recent timestamp of a cache block across all caches.
Definition: memory_system.h:20
bool flushed
Flag to indicate if a cache flushed one of its lines.
Definition: memory_system.h:27
MemorySystem(cache_config &config)
Construct a new memory system.
Definition: memory_system.cc:7
#define MAX_N_CACHES
The maximum number of caches supported by the current trace format (7 bit ID = 128 ID values)
Definition: memory_system.h:9
Configuration for an individual memory system.
Definition: typedefs.h:164
Global type definitions.
uint32_t addr_t
Memory address.
Definition: typedefs.h:147
bus_msg_e
Bus message IDs.
Definition: typedefs.h:92