CohereSim: A Bus-based Cache Simulator  v3.3
A tool for education in computing - learn about coherence protocols, replacement policies, and SMP vs DSM
coherence_protocol.h
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1 
4 #pragma once
5 
6 #include "cache_abc.h"
7 
9 #define STATE_ERR std::cerr << __FILE__ << ':' << __FUNCTION__ << ": Cache line in invalid state: " << (int)(line->state) << std::endl
11 #define UNIMPLEMENTED std::cerr << "Call of unimplemented bus message: " << __FUNCTION__ << std::endl; return false
12 
15 public:
16 
20  virtual ~CoherenceProtocol() {}
21 
24  virtual void PrRd(cache_line* line) = 0;
27  virtual void PrWr(cache_line* line) = 0;
28 
32  virtual bool BusRd(cache_line* line) = 0;
36  virtual bool BusRdX(cache_line* line) { UNIMPLEMENTED; };
40  virtual bool BusUpdt(cache_line* line) { UNIMPLEMENTED; };
44  virtual bool BusUpgr(cache_line* line) { UNIMPLEMENTED; };
48  virtual bool BusWr(cache_line* line) { UNIMPLEMENTED; };
49 
52  virtual bool doesDirtySharing() { return false; }
55  virtual bool doesWriteNoAllocate() { return false; }
56 
60  virtual bool isWriteBackNeeded(state_e state) = 0;
61 
62 protected:
63 
66 };
67 
70 #define ADD_COHERENCE_TO_CMD_LINE(coh_prot) static int register_coherence = []() { \
71 if (coherence_map == nullptr) coherence_map = new std::map<std::string, coh_factory_t, ci_less>(); \
72 (*coherence_map)[#coh_prot] = [](CacheABC& cache) { return new coh_prot(cache); }; return 0; }()
Declaration of the cache interface class.
The cache interface.
Definition: cache_abc.h:9
The base class for coherence protocols.
Definition: coherence_protocol.h:14
CacheABC & cache
The parent cache.
Definition: coherence_protocol.h:65
virtual bool isWriteBackNeeded(state_e state)=0
Determine whether a line needs to be written back to main memory.
virtual bool BusUpgr(cache_line *line)
Receive a BusUpgr message.
Definition: coherence_protocol.h:44
virtual bool doesDirtySharing()
Determine whether the coherence protocol does dirty sharing.
Definition: coherence_protocol.h:52
virtual bool doesWriteNoAllocate()
Determine whether the coherence protocol uses write no-allocate.
Definition: coherence_protocol.h:55
virtual void PrRd(cache_line *line)=0
Receive a PrRd message.
virtual bool BusWr(cache_line *line)
Receive a BusWr message.
Definition: coherence_protocol.h:48
virtual bool BusRdX(cache_line *line)
Receive a BusRdX message.
Definition: coherence_protocol.h:36
CoherenceProtocol(CacheABC &cache)
Construct a new coherence protocol.
Definition: coherence_protocol.h:19
virtual bool BusUpdt(cache_line *line)
Receive a BusUpdt message.
Definition: coherence_protocol.h:40
virtual void PrWr(cache_line *line)=0
Receive a PrWr message.
virtual bool BusRd(cache_line *line)=0
Receive a BusRd message.
#define UNIMPLEMENTED
Error message printed when a cache issues a bus message not supported by the coherence protocol.
Definition: coherence_protocol.h:11
Cache line fields (without data field)
Definition: typedefs.h:152
state_e
Cache line state.
Definition: typedefs.h:64