CohereSim: A Bus-based Cache Simulator
v3.3
A tool for education in computing - learn about coherence protocols, replacement policies, and SMP vs DSM
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The base class for coherence protocols. More...
#include <coherence_protocol.h>
Public Member Functions | |
CoherenceProtocol (CacheABC &cache) | |
Construct a new coherence protocol. More... | |
virtual void | PrRd (cache_line *line)=0 |
Receive a PrRd message. More... | |
virtual void | PrWr (cache_line *line)=0 |
Receive a PrWr message. More... | |
virtual bool | BusRd (cache_line *line)=0 |
Receive a BusRd message. More... | |
virtual bool | BusRdX (cache_line *line) |
Receive a BusRdX message. More... | |
virtual bool | BusUpdt (cache_line *line) |
Receive a BusUpdt message. More... | |
virtual bool | BusUpgr (cache_line *line) |
Receive a BusUpgr message. More... | |
virtual bool | BusWr (cache_line *line) |
Receive a BusWr message. More... | |
virtual bool | doesDirtySharing () |
Determine whether the coherence protocol does dirty sharing. More... | |
virtual bool | doesWriteNoAllocate () |
Determine whether the coherence protocol uses write no-allocate. More... | |
virtual bool | isWriteBackNeeded (state_e state)=0 |
Determine whether a line needs to be written back to main memory. More... | |
Protected Attributes | |
CacheABC & | cache |
The parent cache. | |
The base class for coherence protocols.
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inline |
Construct a new coherence protocol.
cache | The parent cache |
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pure virtual |
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inlinevirtual |
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inlinevirtual |
Receive a BusUpdt message.
line | The cache line accessed |
Reimplemented in Dragon.
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inlinevirtual |
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inlinevirtual |
Receive a BusWr message.
line | The cache line accessed |
Reimplemented in WriteThrough.
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inlinevirtual |
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inlinevirtual |
Determine whether the coherence protocol uses write no-allocate.
Reimplemented in WriteThrough.
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pure virtual |
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pure virtual |
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pure virtual |