CohereSim: A Bus-based Cache Simulator  v3.3
A tool for education in computing - learn about coherence protocols, replacement policies, and SMP vs DSM
mesi.h
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1 
4 #pragma once
5 
6 #include "coherence_protocol.h"
7 
9 class MESI : public CoherenceProtocol {
10 public:
11 
15 
18  void PrRd(cache_line* line);
21  void PrWr(cache_line* line);
22 
26  bool BusRd(cache_line* line);
30  bool BusRdX(cache_line* line);
34  bool BusUpgr(cache_line* line);
35 
39  bool isWriteBackNeeded(state_e state);
40 };
The cache interface.
Definition: cache_abc.h:9
The base class for coherence protocols.
Definition: coherence_protocol.h:14
CacheABC & cache
The parent cache.
Definition: coherence_protocol.h:65
The MESI coherence protocol.
Definition: mesi.h:9
bool BusRd(cache_line *line)
Receive a BusRd message.
Definition: mesi.cc:41
void PrRd(cache_line *line)
Receive a PrRd message.
Definition: mesi.cc:8
MESI(CacheABC &cache)
Construct a new MESI coherence protocol.
Definition: mesi.h:14
void PrWr(cache_line *line)
Receive a PrWr message.
Definition: mesi.cc:23
bool BusRdX(cache_line *line)
Receive a BusRdX message.
Definition: mesi.cc:56
bool isWriteBackNeeded(state_e state)
Determine whether a line needs to be written back to main memory.
Definition: mesi.cc:83
bool BusUpgr(cache_line *line)
Receive a BusUpgr message.
Definition: mesi.cc:71
Definition of the coherence protocol base class.
Cache line fields (without data field)
Definition: typedefs.h:152
state_e
Cache line state.
Definition: typedefs.h:64