The cache interface.
Definition: cache_abc.h:9
The base class for coherence protocols.
Definition: coherence_protocol.h:14
CacheABC & cache
The parent cache.
Definition: coherence_protocol.h:65
The WriteThrough coherence protocol.
Definition: write_through.h:9
bool BusRd(cache_line *line)
Receive a BusRd message.
Definition: write_through.cc:36
void PrRd(cache_line *line)
Receive a PrRd message.
Definition: write_through.cc:8
WriteThrough(CacheABC &cache)
Construct a new WriteThrough coherence protocol.
Definition: write_through.h:14
void PrWr(cache_line *line)
Receive a PrWr message.
Definition: write_through.cc:22
bool BusWr(cache_line *line)
Receive a BusWr message.
Definition: write_through.cc:47
bool doesWriteNoAllocate()
Determine whether the coherence protocol uses write no-allocate.
Definition: write_through.cc:59
bool isWriteBackNeeded(state_e state)
Determine whether a line needs to be written back to main memory.
Definition: write_through.cc:63
Definition of the coherence protocol base class.
Cache line fields (without data field)
Definition: typedefs.h:152
state_e
Cache line state.
Definition: typedefs.h:64