CohereSim: A Bus-based Cache Simulator  v3.3
A tool for education in computing - learn about coherence protocols, replacement policies, and SMP vs DSM
cache.h
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1 
4 #pragma once
5 
6 #include "cache_abc.h"
7 
9 class Cache : public CacheABC {
10 public:
11 
17  ~Cache();
18 
21  void receivePrRd(addr_t addr);
24  void receivePrWr(addr_t addr);
25 
29  bool issueBusMsg(bus_msg_e bus_msg);
33  void receiveBusMsg(bus_msg_e bus_msg, addr_t addr);
34 
39  state_e getLineState(uint32_t set_idx, uint32_t way_idx);
40 
41 #ifdef WRITE_TIMESTAMP
45  size_t getTimestamp(addr_t addr);
46 #endif
47 
50  void printStats();
51 
52 private:
53 
58 
65 
67  uint32_t cache_id;
69  uint32_t num_sets;
71  uint32_t line_offset;
73  uint32_t tag_offset;
74 
76  size_t statistics[N_STATISTICS] = { 0 };
77 
82 
86  void stateChangeStatistic(state_e before, state_e after);
87 
92  cache_line* allocate(addr_t addr);
96  cache_line* findLine(addr_t addr);
97 };
Declaration of the cache interface class.
The cache interface.
Definition: cache_abc.h:9
An L1 Cache with coherence protocol and replacement policy.
Definition: cache.h:9
uint32_t num_sets
The number of sets in the cache.
Definition: cache.h:69
size_t getTimestamp(addr_t addr)
Get the access number of the most recent edit to a cache line.
Definition: cache.cc:192
Cache(MemorySystem &memory_system, uint32_t cache_id, cache_config &config)
Construct a new cache.
Definition: cache.cc:11
uint32_t tag_offset
Number of bits that come before the tag field.
Definition: cache.h:73
void receivePrRd(addr_t addr)
Issue a PrRd message to this cache.
Definition: cache.cc:38
MemorySystem & memory_system
Parent memory system.
Definition: cache.h:55
void receiveBusMsg(bus_msg_e bus_msg, addr_t addr)
Issue a bus message to this cache.
Definition: cache.cc:128
state_e getLineState(uint32_t set_idx, uint32_t way_idx)
Get the state of a line in the cache.
Definition: cache.cc:187
uint32_t line_offset
Number of bits that come before the line offset field.
Definition: cache.h:71
cache_line * lines
Cache lines contained in this cache.
Definition: cache.h:64
ReplacementPolicy * replacement_policy
Replacement policy used by this cache.
Definition: cache.h:62
size_t statistics[N_STATISTICS]
Cache runtime statistics.
Definition: cache.h:76
bool issueBusMsg(bus_msg_e bus_msg)
Issue a BusRd message to neighboring caches.
Definition: cache.cc:104
CoherenceProtocol * coherence_protocol
Coherence protocol used by this cache.
Definition: cache.h:60
cache_config & config
Config from the parent memory system.
Definition: cache.h:57
void printStats()
Print simulation run statistics in CSV format (headerless)
Definition: cache.cc:199
cache_line * allocate(addr_t addr)
Initialize a line in the cache, performing a writeback if necessary.
Definition: cache.cc:221
void receivePrWr(addr_t addr)
Issue a PrWr message to this cache.
Definition: cache.cc:69
addr_t curr_access_addr
The address being accessed by the current processor read or write.
Definition: cache.h:81
cache_line * findLine(addr_t addr)
Locate a line in the cache.
Definition: cache.cc:242
void stateChangeStatistic(state_e before, state_e after)
Update the correct state transition statistic.
Definition: cache.cc:210
uint32_t cache_id
ID of this cache.
Definition: cache.h:67
The base class for coherence protocols.
Definition: coherence_protocol.h:14
The MemorySystem class connecting multiple caches and main memory.
Definition: memory_system.h:12
The base class for replacement policies.
Definition: replacement_policy.h:9
Configuration for an individual memory system.
Definition: typedefs.h:164
Cache line fields (without data field)
Definition: typedefs.h:152
state_e
Cache line state.
Definition: typedefs.h:64
@ N_STATISTICS
The number of statistics a cache keeps track of; not a statistic.
Definition: typedefs.h:143
uint32_t addr_t
Memory address.
Definition: typedefs.h:147
bus_msg_e
Bus message IDs.
Definition: typedefs.h:92