docs/CohereSim/msi_8h_source.html

 #pragma once


 #include "coherence_protocol.h"


 class MSI : public CoherenceProtocol {

 public:


     MSI(CacheABC& cache) : CoherenceProtocol(cache) {}


     void PrRd(cache_line* line);

     void PrWr(cache_line* line);


     bool BusRd(cache_line* line);

     bool BusRdX(cache_line* line);


     bool isWriteBackNeeded(state_e state);

 };

CacheABC
The cache interface.
Definition: cache_abc.h:9

CoherenceProtocol
The base class for coherence protocols.
Definition: coherence_protocol.h:14

CoherenceProtocol::cache
CacheABC & cache
The parent cache.
Definition: coherence_protocol.h:65

MSI
The MSI coherence protocol.
Definition: msi.h:9

MSI::isWriteBackNeeded
bool isWriteBackNeeded(state_e state)
Determine whether a line needs to be written back to main memory.
Definition: msi.cc:66

MSI::BusRd
bool BusRd(cache_line *line)
Receive a BusRd message.
Definition: msi.cc:37

MSI::PrWr
void PrWr(cache_line *line)
Receive a PrWr message.
Definition: msi.cc:23

MSI::MSI
MSI(CacheABC &cache)
Construct a new MSI coherence protocol.
Definition: msi.h:14

MSI::PrRd
void PrRd(cache_line *line)
Receive a PrRd message.
Definition: msi.cc:8

MSI::BusRdX
bool BusRdX(cache_line *line)
Receive a BusRdX message.
Definition: msi.cc:51

coherence_protocol.h
Definition of the coherence protocol base class.

cache_line
Cache line fields (without data field)
Definition: typedefs.h:152

state_e
state_e
Cache line state.
Definition: typedefs.h:64