CohereSim: A Bus-based Cache Simulator
v3.3
A tool for education in computing - learn about coherence protocols, replacement policies, and SMP vs DSM
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The MSI coherence protocol. More...
#include <msi.h>
Public Member Functions | |
MSI (CacheABC &cache) | |
Construct a new MSI coherence protocol. More... | |
void | PrRd (cache_line *line) |
Receive a PrRd message. More... | |
void | PrWr (cache_line *line) |
Receive a PrWr message. More... | |
bool | BusRd (cache_line *line) |
Receive a BusRd message. More... | |
bool | BusRdX (cache_line *line) |
Receive a BusRdX message. More... | |
bool | isWriteBackNeeded (state_e state) |
Determine whether a line needs to be written back to main memory. More... | |
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CoherenceProtocol (CacheABC &cache) | |
Construct a new coherence protocol. More... | |
virtual bool | BusUpdt (cache_line *line) |
Receive a BusUpdt message. More... | |
virtual bool | BusUpgr (cache_line *line) |
Receive a BusUpgr message. More... | |
virtual bool | BusWr (cache_line *line) |
Receive a BusWr message. More... | |
virtual bool | doesDirtySharing () |
Determine whether the coherence protocol does dirty sharing. More... | |
virtual bool | doesWriteNoAllocate () |
Determine whether the coherence protocol uses write no-allocate. More... | |
Additional Inherited Members | |
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CacheABC & | cache |
The parent cache. | |
The MSI coherence protocol.
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inline |
Construct a new MSI coherence protocol.
cache | The parent cache |
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virtual |
Receive a BusRd message.
line | The cache line accessed |
Implements CoherenceProtocol.
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virtual |
Receive a BusRdX message.
line | The cache line accessed |
Reimplemented from CoherenceProtocol.
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virtual |
Determine whether a line needs to be written back to main memory.
state | The state of the line |
Implements CoherenceProtocol.
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virtual |
Receive a PrRd message.
line | The cache line accessed (non-null) |
Implements CoherenceProtocol.
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virtual |
Receive a PrWr message.
line | The cache line accessed (non-null) |
Implements CoherenceProtocol.