CohereSim: A Bus-based Cache Simulator  v3.3
A tool for education in computing - learn about coherence protocols, replacement policies, and SMP vs DSM
typedefs.h
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1 
4 #pragma once
5 
6 #include <cstdint>
7 #include <cstring>
8 #include <functional>
9 #include <iomanip>
10 #include <iostream>
11 #include <map>
12 
13 #ifndef N_INTERACTIVE_MODE_LINES
15 #define N_INTERACTIVE_MODE_LINES 5
16 #endif
17 #if N_INTERACTIVE_MODE_LINES > 9
18 #error("N_INTERACTIVE_MODE_LINES must be a single digit number")
19 #endif
20 
22 class Cache;
24 class CacheABC;
26 class CoherenceProtocol;
28 class MemorySystem;
30 class ReplacementPolicy;
31 
34  ARG_S_PROG,
35  ARG_CACHE_SIZE,
36  ARG_LINE_SIZE,
37  ARG_ASSOCIATIVITY,
38  ARG_COHERENCE,
39  ARG_REPLACEMENT,
40  ARG_DIRECTORY,
41  ARG_C_COUNT,
42  ARG_S_TRACE_FILE = ARG_C_COUNT,
43  ARG_S_TRACE_LIMIT,
44  ARG_S_COUNT
45 };
46 
49  ARG_M_PROG,
50  ARG_CONFIG,
51  ARG_M_TRACE_FILE,
52  ARG_M_TRACE_LIMIT,
53  ARG_M_COUNT
54 };
55 
58  ARG_I_PROG,
59  ARG_INTERACTIVE,
60  ARG_I_COUNT
61 };
62 
64 enum state_e {
68  I = 0,
69 
70  /* Exclusive states */
72  D,
74  E,
76  M,
78  V,
79 
80  /* Shared states */
82  O,
84  S,
86  Sc,
88  Sm
89 };
90 
92 enum bus_msg_e {
97 
108 
110  N_MESSAGES
111 };
112 
117  ReadMiss = N_MESSAGES, // Continuation of 'bus_msg_e'
120 
131 
134 
141 
144 };
145 
147 typedef uint32_t addr_t;
149 typedef uint32_t tag_t;
150 
152 struct cache_line {
157 #ifdef WRITE_TIMESTAMP
159  size_t timestamp;
160 #endif
161 };
162 
164 struct cache_config {
166  uint32_t id;
168  uint32_t cache_size;
170  uint32_t line_size;
172  uint32_t assoc;
174  std::string coherence;
176  std::string directory;
178  std::string replacer;
179 };
180 
182 struct ci_less {
187  bool operator() (const std::string& s1, const std::string& s2) const;
188 };
189 
190 #pragma pack(push, 1)
192 struct trace_t {
194  uint8_t op;
197 };
198 #pragma pack(pop)
199 
201 typedef std::function<CoherenceProtocol* (CacheABC&)> coh_factory_t;
203 typedef std::function<MemorySystem* (cache_config&)> dir_factory_t;
205 typedef std::function<ReplacementPolicy* (CacheABC&, uint32_t, uint32_t)> rep_factory_t;
206 
208 extern std::map<std::string, coh_factory_t, ci_less>* coherence_map;
210 extern std::map<std::string, dir_factory_t, ci_less>* directory_map;
212 extern std::map<std::string, rep_factory_t, ci_less>* replacement_map;
The cache interface.
Definition: cache_abc.h:9
An L1 Cache with coherence protocol and replacement policy.
Definition: cache.h:9
The base class for coherence protocols.
Definition: coherence_protocol.h:14
The MemorySystem class connecting multiple caches and main memory.
Definition: memory_system.h:12
The base class for replacement policies.
Definition: replacement_policy.h:9
Configuration for an individual memory system.
Definition: typedefs.h:164
uint32_t line_size
The line size of each L1 cache.
Definition: typedefs.h:170
std::string coherence
The name of the coherence protocol.
Definition: typedefs.h:174
std::string replacer
The name of the replacement policy.
Definition: typedefs.h:178
uint32_t assoc
The associativity of each L1 cache.
Definition: typedefs.h:172
uint32_t cache_size
The size of each L1 cache.
Definition: typedefs.h:168
uint32_t id
The id for this configuration.
Definition: typedefs.h:166
std::string directory
The name of the directory protocol.
Definition: typedefs.h:176
Cache line fields (without data field)
Definition: typedefs.h:152
tag_t tag
Tag of the line.
Definition: typedefs.h:154
size_t timestamp
The timestamp of the last write to the cache line.
Definition: typedefs.h:159
state_e state
State the line is in.
Definition: typedefs.h:156
Comparator functor for strings, case insensitive.
Definition: typedefs.h:182
bool operator()(const std::string &s1, const std::string &s2) const
Compare two string ignoring case.
Definition: main.cc:216
The format of a single trace.
Definition: typedefs.h:192
uint8_t op
The first byte of a trace; the 7-bit CPU ID combined with the 1-bit R/W mode.
Definition: typedefs.h:194
addr_t addr
The address that is accessed.
Definition: typedefs.h:196
std::function< CoherenceProtocol *(CacheABC &)> coh_factory_t
Coherence protocol factory function signature.
Definition: typedefs.h:201
std::map< std::string, rep_factory_t, ci_less > * replacement_map
A map from replacement policy names to their factory functions.
Definition: main.cc:21
std::function< ReplacementPolicy *(CacheABC &, uint32_t, uint32_t)> rep_factory_t
Replacement policy factory function signature.
Definition: typedefs.h:205
state_e
Cache line state.
Definition: typedefs.h:64
@ Unallocated
Alias for invalid, used in protocols that don't invalidate.
Definition: typedefs.h:66
@ V
Valid exclusive.
Definition: typedefs.h:78
@ M
Modified exclusive.
Definition: typedefs.h:76
@ D
Dirty exclusive.
Definition: typedefs.h:72
@ Sc
Shared clean.
Definition: typedefs.h:86
@ E
Clean exclusive.
Definition: typedefs.h:74
@ Sm
Shared modified.
Definition: typedefs.h:88
@ I
Invalid.
Definition: typedefs.h:68
@ S
Shared.
Definition: typedefs.h:84
@ O
Owned.
Definition: typedefs.h:82
statistic_e
Cache runtime statistic IDs.
Definition: typedefs.h:115
@ LineFlush
Cache line data broadcasted across memory bus.
Definition: typedefs.h:122
@ LineFetch
Cache line data retrieved from main memory.
Definition: typedefs.h:124
@ Invalidation
Cache line state set to invalid (I)
Definition: typedefs.h:140
@ WriteMiss
Write miss on a cache line.
Definition: typedefs.h:119
@ Eviction
Cache line evicted by the replacement policy.
Definition: typedefs.h:133
@ Intervention
Cache line changes from singular (D, E, M, V) to shared (O, S, Sc, Sm)
Definition: typedefs.h:138
@ N_STATISTICS
The number of statistics a cache keeps track of; not a statistic.
Definition: typedefs.h:143
@ CacheToCache
Transfer between two caches.
Definition: typedefs.h:126
@ Exclusion
Cache line changes from shared (O, S, Sc, Sm) to singular (D, E, M, V)
Definition: typedefs.h:136
@ WriteMemory
Direct write from CPU to main memory.
Definition: typedefs.h:130
@ ReadMiss
Read miss on a cache line.
Definition: typedefs.h:117
@ WriteBack
Cache line data written to main memory.
Definition: typedefs.h:128
args_interactive_e
Argument indices for interactive mode.
Definition: typedefs.h:57
args_batch_e
Argument indices for multiple metrics run.
Definition: typedefs.h:48
uint32_t addr_t
Memory address.
Definition: typedefs.h:147
bus_msg_e
Bus message IDs.
Definition: typedefs.h:92
@ BusWrite
Bus upgrade message issued by a cache.
Definition: typedefs.h:107
@ BusUpdate
Bus update message issued by a cache.
Definition: typedefs.h:103
@ BusUpgrade
Bus write message issued by a cache.
Definition: typedefs.h:105
@ N_MESSAGES
Number of bus messages.
Definition: typedefs.h:110
@ ProcWrite
Write access on a cache line.
Definition: typedefs.h:96
@ ProcRead
Read access on a cache line.
Definition: typedefs.h:94
@ BusRead
Bus read message issued by a cache.
Definition: typedefs.h:99
@ BusReadX
Bus read-exclusive message issued by a cache.
Definition: typedefs.h:101
args_single_e
Argument indices for single metrics run.
Definition: typedefs.h:33
std::function< MemorySystem *(cache_config &)> dir_factory_t
Directory protocol factory function signature.
Definition: typedefs.h:203
std::map< std::string, coh_factory_t, ci_less > * coherence_map
A map from coherence protocol names to their factory functions.
Definition: main.cc:19
uint32_t tag_t
Cache line tag.
Definition: typedefs.h:149
std::map< std::string, dir_factory_t, ci_less > * directory_map
A map from directory protocol names to their factory functions.
Definition: main.cc:20